SAR imaging of moving targets

A method of forming synthetic aperture radar (SAR) images of moving targets without using any specific knowledge of the target motion is presented. The new method uses a unique processing kernel that involves a one-dimensional interpolation of the deramped phase history which we call keystone formatting. This preprocessing simultaneously eliminates the effects of linear range migration for all moving targets regardless of their unknown velocity. Step two of the moving target imaging technique involves a two-dimensional focusing of the movers to remove residual quadratic range migration errors. The third and last step removes cubic and higher order defocusing terms. This imaging technique is demonstrated using SAR data collected as part of DARPA's Moving Target Exploitation (MTE) program     

聚束SAR扩展Chirp Scaling成像算法.

在合成孔径雷达（SAR Synthetic Aperture Radar)的成像算法中，Chrip Scaling成像算法具有计算效率高的优点，因此得到了较为广泛的应用。详细研究了子孔径扩展Chirp Scaling算法在高分辩率聚束模式SAR中的应用，包括子孔径划分和方位向处理问题，针对A.Moreira等1996年所提算法在处理聚束SAR数据时所产生的问题，给出了经过改进的适合于大斜视角处理的整个计算过程的完整表达式。在给出点目标仿真的同时，利用E-SAR实际数据对述方法进行了验证，结果对具体的兼容条带和聚束两种工作模式的SAR处理机设计具有一定的参考价值。     

基于飞行器的飞行导航与飞行控制数据综合的研究

针对基于双处理器结构的飞控计算机数据综合过程中的时间同步、时间管理问题,采用了初始同步和周期同步相结合的方式,对任务运行中的误差进行了修正,并在时间同步的基础上,将控制链条分解成若干个控制单元进行分时调度,实现了双机并行处理.同时对数据综合过程中的数据处理方式也进行了讨论.     

基于多核DSP的多波形管理设计

在使用多核处理器进行航空电子系统综合化设计时,各波形供应商通常因为各种限制,难以进行波形功能深度综合,因此目前的综合化仅仅是处理资源集中放置,并未很好地发挥多核处理器的效能。本文基于TI公司多核DSP,设计了一种多波形管理框架,可以将多个无线电波形集中在一个多核DSP中灵活部署、运行并管理,充分发挥多核处理器运算能力,提高系统资源利用率。     

基于时钟驱动的循环调度

实时系统,诸如航空电子系统、空中交通控制系统(Air Traffic Control: ATC)等,从本质上说都是一种分布式实时系统,从理论上说,它们由三种类型的处理器组成,包括数据控制处理器、数据传输处理器和数据处理器.无论是数据控制处理器和数据处理器的数据计算任务,还是数据传输处理器的数据传输任务,它们的执行都必须满足任务的时间约束要求,从而正确完成系统设计的各项应用任务.本文将描述基于时钟驱动的循环调度策略,它不仅适用于对数据计算任务的实时调度,也适用于对数据传输任务的实时调度,最后,分析了此调度策略应用中存在的优势与劣势.     

Optimal divisible job load sharing for bus networks

Optimal load allocation for load sharing a divisible job over N processors interconnected in bus-oriented network is considered. The processors are equipped with front-end processors. It is analytically proved, for the first time, that a minimal solution time is achieved when the computation by each processor finishes at the same time. Closed form solutions for the minimum finish time and the optimal data allocation for each processor are also obtained     

Properties of Dolph-Chebyshev Weighting Functions

Dolph-Chebyshev amplitude weighting is used with FFT signal processors and array antennas when a low sidelobe response is required. This particular weighting minimizes the width of the mainlobe response while forcing all of the sidelobes to a specified sidelobe level. As the specified sidelobe level is reduced, the mainlobe width increases, as does the loss in signal-to-noise ratio. This correspondence describes how the Dolph-Chebyshev weights may be easily calculated, and gives design data showing how signal-to-noise loss and mainlobe width vary with the specified sidelobe level.     

A parallel computer architecture for continuous simulation

A parallel computer specifically designed for the solution of ordinary differential equations is described. The first version of the machine contains thirty-two processors, running in an asynchronous multiple-instruction/multiple-data mode, communicating with high-speed parallel busses. Synchronization is accomplished by a microprogrammable communication controller. A number of processors have been designed and built for the machine. The processor types offer a wide variation in solution speed and accuracy. To permit easy comparisons with analog and hybrid systems, performance is measured by finding the highest frequency sine wave which can be integrated in real time with an accuracy of 0.1% or higher. Using this performance measure the performance limit of the current machine is 2000 Hz. The structure is capable of solving systems described by differential equations up to order sixty-four at these performance limits     

uClinux的XIP执行方式研究

uClinux是主流Linux的一个变种,它运行于无MMU(内存管理单元)的处理器架构之上.分析了uClinux内核的组成并对实现uClinux的XIP(Execute-In-Place)运行的关键技术进行了深入研究,改进了代码重定位问题的算法,进而实现uClinux在基于ARM平台上的移植和XIP运行.这样内核代码段和应用程序可以直接从Flash或ROM中运行,减少内存需求.     

A chirp scaling approach for processing squint mode SAR data

Image formation from squint mode synthetic aperture radar (SAR) is limited by image degradations caused by neglecting the range-variant filtering required by secondary range compression (SRC). Introduced here is a nonlinear FM chirp scaling, an extension of the chirp scaling algorithm, as an efficient and accurate approach to range variant SRC. Two methods of implementing the approach are described. The nonlinear FM filtering method is more accurate but adds a filtering step to the chirp scaling algorithm, although the extra computation is less than that of a time domain residual compression filter. The nonlinear FM pulse method consists of changing the phase modulation of the transmitted pulse, thus avoiding an increase in computation. Simulations show both methods significantly improve resolution width and sidelobe level, compared with existing SAR processors for squint angles above 10 deg for L-band and 20 deg for C-band     

Performance limits for processor networks with divisible jobs

Ultimate performance limits to the aggregate processing speed of networks of processors that are processing a divisible job are described. These take the form of either closed-form expressions or numerical procedures to calculate the equivalent processing speed of an infinite number of processors. These processors are interconnected in either a linear daisy chain with load origination from the network interior or a tree topology. The tree topology is particularly general as a natural way to perform load distribution in a professor network topology with cycles (e.g., hypercube, toroidal network) is to use an embedded spanning tree. Such limits on performance are important as they provide an ideal baseline against which to compare the performance of finite configurations of processors.     

Distributed computation with communication delay [distributedintelligent sensor networks]

A linear network of communicating processors is examined. The objective is to solve a computational problem in a minimal amount of time. The processors in the networks may be equipped either with or without front-end processors for communication off-loading. The cases of equal division of processing load and optimal division of processing load are discussed for both the network with front-end processors and the network without front end processors. An example of the inclusion of solution time, the time taken for processors to report the solution back to the problem originator, is also presented     

Software radios: Survey, critical evaluation and future directions

A software radio is defined as a set of digital signal processing (DSP) primitives, a metalevel system for combining the primitives into communication system functions (transmitter, channel model, receiver, etc.), and a set of target processors on which the software radio is hosted for real-time communications. The performance of enabling hardware technologies is related to software radio requirements, portending a decade of shift from hardware radios toward software intensive approaches. Computational models and architecture are discussed, stressing the need for topological consistency of radio functions and host architectures. A layered topology-oriented design approach encapsulated in a canonical open architecture software radio model is presented. The model provides a unified mathematical framework for quantitative analysis of algorithm structures, host architectures, and system performance for CAD     

Task allocation and reallocation for fault tolerance inmulticomputer systems

The goal of task allocation in a set of interconnected processors (computers) is to maximize the efficient use of resources and thus reduce the job turnaround time. Proposed is a simple yet effective method to allocate the tasks in multicomputer systems for minimizing the interprocessor communication cost subject to resource limitations defined by the system and designer. The limitations can be viewed as results from the load balancing since the execution time of each task, the number of available processors, processor speed, and memory capacity are known to the system or designer. As the number of processors increases, the probability of a failure existing somewhere in the systems at any time also increases. Very few established task allocation models have considered the reliability property. In multicomputer systems, we define system reliability as the probability that the system can run the tasks successfully. After the (nonredundant) task scheduling strategy is defined, tasks are then reallocated to processors statically and redundantly. This is a form of time redundancy, in which if some processors fail during the execution, all tasks can be completed on the remaining processors (but at a longer time). Due to static preallocation of tasks this method is simpler and thus more practical than well-known dynamic reconfiguration and rollback recovery techniques in multicomputer systems. We demonstrate the effectiveness of the task allocation and reallocation for hardware fault tolerance by illustrations of applying the methods to different examples and practical communications network multiprocessor system     

Analysis and design optimization of monopulse receivers forsecondary surveillance radar

The sensitivity to calibration and component errors of the receiver configurations used for monopulse processing of secondary surveillance radar (SSR) replies is analyzed. The effects of video gain error in amplitude processors and large Gaussian perturbations in phase processors are discussed. Phase processors are shown to be robust to variations in antenna difference pattern null depth. A half-angle phase processor that yields the benefits of phase processing without the sensitivity to system errors associated with conventional implementations is described     

单片机控制下的ARINC429总线通信与EL显示

结合“雷达目标模拟器”这一课题 ,对单片机控制下的ARINC4 2 9总线通信及EL显示进行了研究。模拟器采用 87C5 1单片机作为控制核心 ,应用汇编语言编程。本文着重总结了ARINC4 2 9总线数据接收与EL汉字送显     

面向机载应用的领域专用加速器研究

机载环境下数据处理规模的剧增以及人机混合智能的应用使得传统的以CPU 为核心计算单元的架构 已不能满足计算需求。在满足延时、精度等指标的情况下,选用高能效的处理器或处理器组合来快速准确地处 理这些数据成为机载计算领域面临的重要问题。按照常规处理器、领域专用加速器两大类型对各自主要代表性 处理器的架构特点进行了分析和总结,得出了各类处理器在机载情况下的主要适用场景和应用情况。根据领域 专用的设计思想开发了面向数据关联应用的专用加速器,对数据关联算法中的统计距离计算和分簇处理这两个 计算瓶颈进行了定制化的加速设计,并在基于FPGA 的平台上进行了测试验证,结果表明,加速器对于统计距 离计算的加速效果约为FT2000/4 单核性能的10 倍,对于分簇处理的加速效果约为FT2000/4 单核性能的3 倍, 整体运算速度相比FT2000/4 处理器的单核提升了5 倍。     

Distributed computation for a tree network with communicationdelays

Tree networks of communicating processors are examined with the objective of solving a computational problem in a minimal amount of time. The processors in the networks may be equipped either with or without front-end processors for communicating of loading. The determination of the optimal division of processing load is discussed for the network with and the network without front-end processors. The inclusion of solution time, the time taken for sensors to report the solution back to originator, is discussed     

Processor equivalence for daisy chain load sharing processors

A linear daisy chain of processors in which processor load is divisible and shared among the processors is examined. It is shown that two or more processors can be collapsed into a single equivalent processor. This equivalence allows a characterization of the nature of the minimal time solution, a simple method to determine when to distribute load for linear daisy chain networks of processors without front end communication subprocessors and closed form expressions for the equivalent processing speed of infinitely large daisy chains of processors     

A localized adaptive MTD processor

The problem of achieving the optimum moving target indicator (MTI) detection performance in strong clutter of unknown spectrum when the set of data available to the estimation of clutter statistics is small due to a severely nonhomogeneous environment is studied. A new adaptive implementation, called the Doppler domain localized generalized likelihood ratio processor (DDL-GLR), is proposed, and its detection performance is studied in detail. It is shown that the DDL-GLR is a data-efficient implementation of the high-order optimum detector and has several advantages of practical importance over the adaptive processors