| 时频系统数字锁相技术研究 |
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| 引用本文： | 王鹏宇,杨志刚,郑丽丽.时频系统数字锁相技术研究[J].宇航计测技术,2019,39(5):44-50. |
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| 作者姓名： | 王鹏宇 杨志刚 郑丽丽 |
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| 作者单位： | 1、中国电子科技集团公司第二十七研究所，河南郑州 450047 |
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| 摘 要： | 为了利用外部1PPS信号或10MHz频率信号驯服铷钟或晶振,本文推导建立了数字二阶/三阶锁相环频标模块的仿真模型,对模型中的锁相环、鉴相器量化、DA位数、定点运算、环路更新频率对相位噪声性能的影响等关键问题进行了分析,给出了参数设置依据及仿真结果,完成了频标模块的硬件设计,验证了模型的正确性。
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| 关 键 词： | 数字锁相环 秒脉冲(1PPS) 频率准确度 频率稳定度 |
Study on Digital Phase-Locked Loop in the Time and Frequency System |
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| WANG Peng-yu,YANG Zhi-gang,ZHENG Li-li.Study on Digital Phase-Locked Loop in the Time and Frequency System[J].Journal of Astronautic Metrology and Measurement,2019,39(5):44-50. |
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| Authors: | WANG Peng-yu YANG Zhi-gang ZHENG Li-li |
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| Institution: | 1、The 27; Research Institute of China Electronics Technology Group Corporation,Zhengzhou 450047,China |
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| Abstract: | The construction of the external 1PPS/10MHz disciplined Rubidium/Crystal Oscillator by digital 2/3 order phase-locked loop is described in this paper.The Simulation model of frequency standard component is presented,and some key problems about PLL and digital quantitative are analyzed.The parameters set method and simulation result are showed.The hardware design is completed and the testing result verify the correctness of the simulation model. |
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| Keywords: | Digital Phase-Locked Loop(DPLL) 1 Pulse Per Second(1PPS) Frequency accuracy Frequency stability |
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