| PLC指令预取部件 IPU 的设计与实现 |
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| 引用本文： | 刘振山,胖美云.PLC指令预取部件 IPU 的设计与实现[J].北京航空航天大学学报,1992(3):75-81. |
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| 作者姓名： | 刘振山 胖美云 |
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| 作者单位： | 北京航空航天大学计算机科学与工程系
(刘振山)，北京航空航天大学计算机科学与工程系(胖美云) |
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| 摘 要： | 众所周知,Prolog和Lisp是目前国内外普遍采用的人工智能语言。Prolog和Lisp语言的协处理器就是一个通过硬件环境实现对Prolog和Lisp进行加速执行的硬件系统,具有很大的应用价值及研究前景。本文介绍了Sun工作站的Prolog/Lisp协处理器(PLC)中的指令预取部件(Instruction Prefetch Unit,简称IPU)的性能、工作原理及其技术特点,同时给出了采用FPGA技术对IPU进行集成的技术方案及其较大的应用前景。
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| 关 键 词： | PLC协处理器 指令预取部件 |
THE DESIGN AND IMPLIMENTATION OF THE PLC INSTRUCTION PREFETCH UNIT |
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| Liu Zhenshan Fang Meiyun.THE DESIGN AND IMPLIMENTATION OF THE PLC INSTRUCTION PREFETCH UNIT[J].Journal of Beijing University of Aeronautics and Astronautics,1992(3):75-81. |
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| Authors: | Liu Zhenshan Fang Meiyun |
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| Institution: | Dept. of Computer Sci. and Eng. |
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| Abstract: | It is well known that Prolog and Lisp have widespeadly been adopted in the area of computer artificial intelligence.The Prolog and Lisp Co-processor(PLC) is a hardware system board used on Sun workstation to increase the executive speed of applied programs written in Prolog or Lisp.This paper introduces the Instruction Prefetch Unit(IPU) of the PLC,its performance,its work principle and its technique features.Meanwhile,this paper advances the technique plan,which integrates the IPU with FPGA technique,and points out the bright application future of the technique. |
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| Keywords: | Prolog Lisp Co-processor instruction prefetch unit instruction flow line prefetch line buffer line |
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