基于状态图的周期BIT故障检测与虚警抑制仿真

针对BIT(Built-In Test)技术在装备测试性设计与PHM(Prognostic and Health Management)的应用需求,提出了基于状态图(Stateflow)的周期BIT(PBIT, Periodic BIT)故障检测与虚警抑制仿真方法.分析了周期BIT的特性与虚警问题,给出了周期BIT的仿真原理.在加电BIT的基础上分析了周期BIT的仿真要素及其Stateflow对象的仿真模式,并实现了故障注入、干扰注入和虚警抑制措施的建模,最后给出了周期BIT建模仿真以及仿真输入数据设计流程.以某典型航电模块周期BIT为例,建立了电源板、干扰、周期BIT以及虚警抑制措施的Stateflow仿真模型,仿真结果显示该方法能有效地实现周期BIT故障检测与虚警抑制的动态逻辑过程仿真.

Simulation method for PBIT fault detection and false alarm reduction based on stateflow

Aiming at the application requirements of built-in test (BIT) technology in equipment design for testability and prognostic and health management (PHM), a method of periodic BIT (PBIT) simulation based on stateflow was proposed. The fault detection features and fault alarms problem were analyzed, and the simulation principle of PBIT was given. Based on the simulation of power-on BIT (POBIT), the simulation elements of PBIT were analyzed, as well as the stateflow chart objects simulation mode of those elements, and the modeling of faults injection, interferences injection and false alarm reduction measures were implemented. Finally, the flow of modeling and simulation for PBIT was given, including the flow of simulation input dataset design. A typical avionic module PBIT was taken as the case, the stateflow model of power board, interferences, PBITs and false alarm reduction measures were built. The simulation results show that this method contributes to realizing the dynamic logic process simulation of PBIT in fault detection and false alarm reduction effectively.