低压CMOS折叠共源共栅混频器的设计

基于SMIC 0.18μmCMOS工艺,采用一种折叠共源共栅结构,设计实现了一种低压CMOS折叠共源共栅混频器,解决了传统Gilbert混频器中跨导级与开关级堆叠带来的高电源电压问题,以及在跨导级的高跨导、高线性与开关级的低噪声间进行折衷设计的难题.该混频器核心电路尺寸为165μm×75μm,当射频信号、本振信号和中频信号分别为1575.42MHz、1570MHz和5.42MHz时,仿真表明:该混频器转换增益( G_C )为15dB,双边带噪声系数为12.5dB,输入三阶截断点为-0.4dBm,在1.2V的电源电压条件下,功耗为3.8mW,可用于航空航天领域的电子系统中.

Design of low voltage CMOS folded-cascode mixer

By using the folded-cascode structure, the problem on high supply voltage of the stacking trans-conductance stage and switching-transistor stage was solved, and the trade-off among the high trans-conductance, high linearity of the trans-conductance stage and the low noise of the switching-transistor stage were also realized. Implemented in a SMIC 0.18μm CMOS process, the low-voltage complementary metal-oxide semiconductor (CMOS) folded-cascode mixer (FCM) core has an area of 165μm×75μm. When the frequency of the radio frequency (RF) signal, local oscillator (LO) signal and the intermediate frequency (IF) signal are 1575.42MHz, 1570MHz and 5.42MHz, respectively, the simulation results show that the mixer features a conversion gain ( G_C ) of 15dB, a dual sideband (DSB) noise figure of 12.5dB, a third-order input intercept point (IIP3) of -0.4dBm, and consumes 3.8mW at a power supply voltage of 1.2V. The mixer can be applied to the electronic systems within the realm of the aviation aerospace.