一种图像缩放算法的SoC协同加速设计方法

针对无人机自主着陆的跑道检测、识别、跟踪等视觉算法中需要对大量图像进行缩放处理以便后续计算，但又对实时性要求比较高的情况，根据输入输出像素点的映射关系提出了一种适用于硬件加速的图像缩放算法，简化算法结构的同时利用现场可编程门阵列进行模块硬件功能的设计对算法加速，并采用软硬件协同的体系结构搭建实时图像处理系统。实验结果表明，该缩放算法处理精度高、耗时少，且用硬件逻辑实现后，可以进一步提速171倍，硬化后的系统可以通过摄像头获取图像数据，实时处理后在显示器中显示，达到30帧/s的处理速度，可以应用于实时性要求较高的图像处理算法中。 

SoC collaborative acceleration design method for image scaling algorithm

Aimed at the problem that a large number of images need to be scaled in the visual algorithm for the runway detection, recognition and tracking of the unmanned aerial vehicle with high real-time requirement, a new image scaling algorithm suitable for hardware acceleration is proposed based on the mapping relation of the input-output pixel. By simplifying the algorithm structure and using the field programmable gate array to design the hardware function of the module, the algorithm accelerates, and the real-time image processing system is built by the software and hardware cooperative architecture. The experimental results show that the improved scaling algorithm has high precision and less time consumption, and it can speed up by 171 times with the hardware logic. The hardened system can get the image data through the camera, and the real-time processing is displayed in the monitor, which has 30 frame/s processing speed. It can be applied to the image processing algorithm with high real-time requirement.