LZMA压缩算法FPGA硬件实现

LZMA(Lempel Ziv Markov-chain Algorithm)无损压缩算法在进行数据压缩时速度慢且占用大量的CPU(Central Processing Unit)资源,不能满足实时系统的要求.在改进算法的基础上,采用FPGA(Field Programmable Gate Array)设计了一个LZMA压缩算法硬件加速电路.该电路由LZ77压缩控制器、区间编码控制器和数据读出控制器组成,采用数据乒乓结构、高性能并行匹配结构和流水线处理结构等多种方法提高了LZMA压缩算法的速度,在支持标准LZMA压缩文件格式的同时,将压缩速度提升到近125 Mb/s,相比基于软件的LZMA算法加速10倍,每个时钟处理的相对数据加速近200倍.最后通过基于Virtex-6 FPGA的ML605开发平台验证了硬件加速电路的正确性和可行性.

FPGA hardware implementation of the LZMA compression algorithm

Software-based LZMA (Lempel Ziv Markov-chain algorithm) nondestructive compression algorithm is very slow and consumes too much CPU (central processing unit) resources during the data compression process, as a result it can not meet the requirements of real-time systems. On the basis of the improved algorithm, a hardware accelerator for LZMA was designed with FPGA (field programmable gate array) implementation. The hardware accelerator is composed of LZ77 compressor, range encoder and send out controller. Ping-pong operation, parallel matching method with high performance, pipeline processing structure and other acceleration techniques were used to speed up LZMA compression algorithm. While at the same time, data compressed by the circuit is still compatible with standard LZMA file format. The compression rate of the circuit is speeded up to 125 Mb/s, nearly 10 times faster than that of the software based LZMA. The processing relative data of each clock is speeded up nearly 200 times. Results from the experiments on ML605 basing on a Virtex-6 FPGA development kit, show the accelerator is correct and feasible.