一种新型低功耗SRAM读写辅助电路设计

针对低电压下静态随机存储器（SRAM）出现的读写性能损失的问题，设计了一种应用于低功耗SRAM的两步控制（DSC）的字线电压辅助电路技术，可以同时实现读和写辅助的功能，降低SRAM的最小工作电压从而降低功耗。写辅助通过字线开启前段的字线过驱（WLOD）实现，提高写数据速度和写阈值（WM）；读辅助通过字线开启后段的字线欠驱（WLUD）实现，降低静态噪声，提高稳定性。通过在28 nm互补金属氧化物半导体（CMOS）工艺下，对256 Kbit SRAM进行前仿和后仿仿真验证，结果表明相比于传统结构，应用DSC字线电压技术的SRAM的最小工作电压降低100 mV，写时间减小10%，静态功耗降低30%，版图面积增大4%。 

Design of a novel read and write assisted circuit in low power SRAM

In order to solve the problem of read and write performance loss in Static Random-Access Memory (SRAM) under low voltage, a novel Dual-Step Control (DSC) word-line voltage technique for low power SRAM is designed, which can simultaneously realize read and write performance and reduce the minimum operation voltage of SRAM. Thus the power consumed is reduced. Write-assist implementation uses the Word-Line Over Drive (WLOD) at the beginning of the word-line to reduce the write access time and improve Write Margin (WM). And read-assist implementation uses the Word-Line Under Drive (WLUD) after the WLOD to reduce static noise and increase the stability. A 256 Kbit SRAM pre-sim and post-sim simulation, which is designed in 28 nanometer Complementary Metal Oxide Semiconductor (CMOS) process, demonstrates that DSC-SRAM lowers the minimum operation voltage by 100 mV, reduces the write access time by 10%, decreases the static power by 30%, and increases its layout area by 4%, compared to the conventional SRAM structure.