一种航天接口芯片静电防护电路的软击穿现象

接口阻抗测试是航天产品中对产品状态是否正常来进行判断的常用方法。在航天产品应用中，通常认为接口芯片阻抗测试异常即代表该接口芯片已经失效。本文针对一种LVDS接口发送芯片由静电导致阻抗测试异常，但功能正常的现象进行分析。在元器件失效分析的基础上，定位静电损伤的位置为芯片内部静电防护电路，从而建立了对应的电路模型，对芯片静电损伤的现象进行理论分析。分析说明：该芯片在被静电打击时，其静电防护电路中一个NMOS管受损，但该电路保护了芯片的功能电路，被击穿的NMOS管等效为一个电阻，因此导致阻抗测试异常，但芯片功能电路未受损的现象，为静电软击穿现象。且可认为该芯片在受静电影响后并未失效，相关电路仍具有正常工作的能力。即阻抗异常现象并不是芯片失效的充分条件。

Soft Breakdown Phenomenon of Electrostatic Protection Circuit of Space Interface Chip

Interface impedance test is a common method for judging whether the product status is normal in aerospace products. In the application of aerospace products, it is generally considered that an abnormal impedance test of an interface chip means that the interface chip has failed. The phenomenon is analyzed that the impedance test of an LVDS interface transmitter chip is abnormal due to static electricity but the function is normal. Based on the failure analysis of components, the location of electrostatic damage is determined as the electrostatic protection circuit inside the chip, and the corresponding circuit model is established to theoretically analyze the phenomenon of electrostatic damage to the chip. The analysis shows that: When the chip is struck by static electricity, an NMOS tube in its electrostatic protection circuit is damaged, but this circuit protects the functional circuit of the chip, and the broken NMOS tube is equivalent to a resistor. As a result, the impedance test is abnormal but the functional circuit of the chip is not damaged, which is the phenomenon of electrostatic soft breakdown. It can be also considered that the chip does not fail after being affected by static electricity, and the related circuits can still work normally. Therefore, the impedance anomaly is not a sufficient condition for chip failure.