| 一种高速数字复数乘加器的研制 |
| |
| 引用本文： | 党雅文,赵永波.一种高速数字复数乘加器的研制[J].航空计算技术,2004,34(2):91-94. |
| |
| 作者姓名： | 党雅文 赵永波 |
| |
| 作者单位： | 西安电子科技大学,雷达信号处理重点实验室,陕西,西安,710071 |
| |
| 摘 要： | 复数乘加运算是实时数字信号处理系统经常使用的主要运算之一,随着实时数字信号处理的发展,复乘加的运算速度要求越来越高。本文研制了一种基于复杂可编程逻辑器件(CPLD)的高速数字复乘加器,其复乘加的次数可以用外部的输入信号控制,还可以同时共轭输出。该复乘加器成本低,编程灵活,可根据不同的要求广泛应用于各种数字信号处理系统中。
|
| 关 键 词： | 复乘加 CPLD 运算速度 |
| 文章编号： | 1671-654X(2004)02-0091-04 |
| 修稿时间： | 2004年3月26日 |
Development of a High Speed Digital Complex Multiply_adder |
| |
| DANG Ya-wen,ZHAO Yong-bo.Development of a High Speed Digital Complex Multiply_adder[J].Aeronautical Computer Technique,2004,34(2):91-94. |
| |
| Authors: | DANG Ya-wen ZHAO Yong-bo |
| |
| Abstract: | Complex multiply-adder is one of the operations often used in real time digital signal processing systems, with the development of real time signal processing, the demand for the speed of operation is increasing. This paper develops a high speed complex multiply_adder circuit by using complex programmable logic devices (CPLD). In this complex multiply_adder add times can be controlled by an input signal and the circuit can also output its conjugation at the same time. This design has low cost and easy program, which can be widely used in digital signal processing systems according to different requirements. |
| |
| Keywords: | complex multiply_adder CPLD operational speed |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
|
