一种有效的电路仿真验证技术

由于数字电路设计复杂性的增加以及日益紧迫的设计周期的压力,数字电路仿真模型的混合应用在实际应用中变得越来越重要。首先讨论了这种应用带来的问题以及相应的解决方法,接着介绍了混合仿真模型描述的数字电路进行功能验证的两种方案:以VHDL语言描述为顶层的设计方案和以原理图为顶层的设计方案。数字电路仿真模型的混合应用技术,是一种对于混合仿真模型描述的数字电路进行功能验证的方便、快捷的方法,使用该技术可以大大提高数字电路设计的质量和可靠性。

A Efficient Circuit Simulation Verification Technique

Because of the increase of complexity on designing the digital circuit and the increase of pressure on designing cycle, blended application on the simulation modals of digital circuit has becoming more and more important in the practicing application. This paper discusses the problems on this application and shows a corresponding solution, and presents two ways about function verification for digital circuit described using blended simulation modals: Scheme_1 using VHDL Language for Top Design and Scheme_2 using Principle Chart for Top Design. Blended application technique on the digital circuit simulation model is convenient method for digital circuit function verification . By using this technique ,the quality and reliability on the digital circuit design Jun be improved greatly.