方位降采样滤波器设计和FPGA实现

在SAR(合成孔径雷达)雷达实时信号处理中,为了降低运算量且不影响成象质量,通常需要对输入的距离-方向二维数据在方位上做降采样和滤波处理。为了满足实时处理的需要,本文提出了一种将降采样和方位滤波相结合的设计,以及利用窗函数设计滤波器系数的方法,运用硬件描述语言Verilog HDL构造了一种用现场可编程门阵列FPGA实现降采样滤波器的电路结构,并分析了其性能。该降采样滤波器的降采样率和滤波器阶数可变,可适应多种场合的需要。

Design and FPGA Realization of Azimuth Desaming Fir Filter of SAR Real- time Imaging System

During the SAR radar real - time signal processing, for the tauing or operation umes and are (?) or imaging quality, the input rang - azimuth two dimension data need to be desampled and filtered in the azimuth dimension. For the need of real - time processing, the paper describes a design of combination of desampling and azimuth filtering , and introduces a method of design the FIR filter parameters in a windows function way, and design a decampling FIR filter circuit in HDL language Vrilog , and at last analyzes performance of the circuit. The decampling rate and the filter rank of the design are all variable ,so the design can be used in different condition.