基于DSP和FPGA的视频编码器协同设计与算法优化实现

 采用DSP和FPGA协同技术设计实现了一个高性能的MPEG-4视频编码器。FPGA模块完成视频采集、YUV分离、数据I/O等功能,而使用DSP专一进行视频压缩编码。针对DSP片内资源特点设计了片内存储器数据分配方案,并根据该方案优化了MPEG-4视频压缩的数据流模式。提出了基于宏块空间复杂度的宏块类型判断算法,有效地降低了视频压缩算法的计算复杂度。测试结果表明,采用MPEG-4视频标准该视频编码器每秒能够压缩39.2帧CIF图像。

Hardware Design and Algorithm Optimization of Video Encoder Based on DSP and FPGA Techniques

With the development of video encoding techniques, video compression algorithms become more complicated. A real-time high resolution video encoder cannot be implemented with a single CPU or DSP. A MPEG-4 video encoder is designed and implemented based on coordinated DSP and FPGA techniques. The FPGA module takes the tasks of video acquisition, YUV separation and data I/O functions, while the DSP is dedicated for video compression. The data flow scheme of the MPEG-4 video compression is optimized by utilizing the DSP's on-chip memory. A Macro Block (MB) type judging algorithm is proposed based on MB's space complexity. It reduces effectively the computational complexity of the video compression. The experimental results indicate that the MPEG-4 video encoder implementation can encode 39.2 f/s in CIF resolution.