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基于FPGA的北斗B1频点接收机 基带信号处理器设计
引用本文:尚斌斌,赵伟,刘建业,李荣冰,薛涛.基于FPGA的北斗B1频点接收机 基带信号处理器设计[J].导航与控制,2016(4):70-75.
作者姓名:尚斌斌  赵伟  刘建业  李荣冰  薛涛
作者单位:南京航空航天大学导航研究中心,南京,210016
摘    要:针对北斗二代B1频点信号比特翻转频繁的问题,设计并实现了基于FPGA的北斗B1频点导航接收机基带处理器.该处理器在信号捕获过程中设计了频率精细搜索的精捕获算法,避免了假捕获并且提高了捕获频率的精度;在载波跟踪环路中设计2阶锁频环辅助3阶锁相环的方案,以提高环路跟踪的动态性能.其中,锁频环和锁相环均设计了对比特翻转敏感的鉴别器,保证环路跟踪的准确性.试验结果表明,该基带处理器设计具有较高精度的捕获频率和良好的高动态跟踪能力.

关 键 词:北斗B1频点  FPGA  基带处理器  精捕获  比特翻转

The Design of FPGA-based Baseband Signal Processor for BeiDou Receiver on B1 Frequency
SHANG Bin-bin,ZHAO Wei,LIU Jian-ye,LI Rong-bing and XUE Tao.The Design of FPGA-based Baseband Signal Processor for BeiDou Receiver on B1 Frequency[J].Navigation and Control,2016(4):70-75.
Authors:SHANG Bin-bin  ZHAO Wei  LIU Jian-ye  LI Rong-bing and XUE Tao
Institution:Navigation Research Center,Nanjing University of Aeronautics and Astronautics;Navigation Research Center,Nanjing University of Aeronautics and Astronautics;Navigation Research Center,Nanjing University of Aeronautics and Astronautics;Navigation Research Center,Nanjing University of Aeronautics and Astronautics;Navigation Research Center,Nanjing University of Aeronautics and Astronautics
Abstract:To address the problem brought by frequently bit-flipping, the baseband signal processor based on FPGA for BeiDou navigation receiver on B1 frequency is designed and realized. In the process of signal capture, fine capture algorithm for accurate frequency is produced, which avoids the false capture and enhances the sensitivity of capture. Besides, the scheme of second order frequency-locked loop auxiliary third-order phase-locked loop for is proposed to improve dynamic performance of carrier tracking loop, and the discriminators are sensitive to bit-flipping, which can ensure the validity of the tracking results. The test results demonstrate that the processor can perform high precision in capture frequency and good ability in high dynamic tracking.
Keywords:BeiDou B1  FPGA  baseband signal processor  fine capture  bit-flipping
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