FPGA设计中的亚稳态问题及其预防方法研究

由于在复杂FPGA（Field Programmable Gate Array,现场可编程门阵列）设计中存在跨时钟域,通常会产生亚稳态现象.为有效地预防和解决该问题,分析FPGA设计中亚稳态的产生机理及其对数字信号处理系统的影响.根据不同的信号同步类型,针对单比特电平信号、脉冲信号和边沿信号,分别给出基于触发器级联的跨时钟域信号同步方法;针对并行信号,提出基于异步FIFO （First In First Out,先进先出队列）和握手协议的跨时钟域同步方法;并通过仿真手段分析信号同步方法的有效性及其适用范围.结果表明：这些方法能够正确有效地完成跨时钟域信号同步,预防可能出现的亚稳态问题,从而提高复杂FPGA设计的可靠性和稳定性.

Research on Metastability and Its Mitigation Methods in FPGA Design

Metastability is a common problem caused by clock domain crossing in complex FPGA （Field Programma- ble Gate Array） design. To effectively prevent and solve the problem, the trigger mechanism of metastability and its impact on digital signal processing systems is analyzed. Based on signal type, synchronization methods for level sig- nal, pulse signal and edge signal for one-bit signals are proposed. For parallel signals, synchronization methods based on asynchronous FIFO （First In First Out） and hand-shake are proposed. Simulation is done to verify validity of the synchronization methods and to determine their applicability, and the results show that the methods are effec- tive to deal with clock domain crossing signal synchronization, and to help prevent metastability problems and im- prove the reliability and stability of complex FPGA systems.