| 一种采用收发双缓冲结构的1553B总线接口的设计与实现 |
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| 引用本文： | 石然,张永杰,王金芳,饶范钧,徐挺.一种采用收发双缓冲结构的1553B总线接口的设计与实现[J].导航定位于授时,2018,5(5):83-89. |
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| 作者姓名： | 石然 张永杰 王金芳 饶范钧 徐挺 |
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| 作者单位： | 上海航天控制技术研究所;上海惯性工程技术研究中心 |
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| 基金项目： | 上海市优秀技术带头人资助项目（15XD1521500） |
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| 摘 要： | 从简化结构、提高实时性的角度出发,提出了一种RT模式下的1553B总线接口。该总线接口硬件上以BU-61580为总线协议处理器,以FPGA为主处理器,在FPGA内部实现接口粘合逻辑,省去额外电路,做到无缝链接。软件上在接收端采用子地址双缓冲模式,保证数据一致性和正确性,发送端提出了发送双缓冲机制,在保证可靠性的前提下提高了数据更新的实时性。详细阐述了总线接口的设计和实现方案,并通过仿真和实验手段证明了该接口方案的可行性和有效性。
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| 关 键 词： | 1553B总线 双缓冲 接口 FPGA BU-61580 实时性 |
Design and Implementation of 1553B BUS with Double Buffering Mode |
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| SHI Ran,ZHANG Yong-jie,WANG Jin-fang,RAO Fan-jun and XU Ting.Design and Implementation of 1553B BUS with Double Buffering Mode[J].Navigation Positioning & Timing,2018,5(5):83-89. |
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| Authors: | SHI Ran ZHANG Yong-jie WANG Jin-fang RAO Fan-jun and XU Ting |
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| Institution: | Shanghai Institute of Spaceflight Control Technology, Shanghai 201109, China; Shanghai Engineering Research Center of Inertial, Shanghai 201109, China,Shanghai Institute of Spaceflight Control Technology, Shanghai 201109, China; Shanghai Engineering Research Center of Inertial, Shanghai 201109, China,Shanghai Institute of Spaceflight Control Technology, Shanghai 201109, China; Shanghai Engineering Research Center of Inertial, Shanghai 201109, China,Shanghai Institute of Spaceflight Control Technology, Shanghai 201109, China; Shanghai Engineering Research Center of Inertial, Shanghai 201109, China and Shanghai Institute of Spaceflight Control Technology, Shanghai 201109, China; Shanghai Engineering Research Center of Inertial, Shanghai 201109, China |
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| Abstract: | A communication interface of 1553B bus working on RT mode is presented to simplify the circuit structure and improve the real-time performance. In hardware design for the interface, the construction based on BU-61580 protocol chip and FPGA host processor is established, in which there is no the logical adhesion circuit needed for it is included in the FPGA. In software design for the interface, the problem of balancing real-time and reliability is solved by the implementation of double buffering mechanism in both receiving and transmitting messages. The design and implementation for the interface circuit of the 1553B bus are described in detail, and the functionality and performance are also verified by practical and simulation results. |
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| Keywords: | 1553B bus Double buffering Circuit interface FPGA BU-61580 Real-time |
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