合理运用SI技术快速收敛高速数字电路设计

随着数字电路集成度和工作频率的不断提高,信号完整性(Signal Integrity, SI)问题在产品研制过程中越来越突出。以惯导系统中的某导航计算机为例,针对故障信号回路,使用仿真软件对其SDRAM时钟信号进行信号完整性仿真,并进行优化设计。通过对比优化前和优化后的仿真与测量结果,验证了由于端接参数不匹配造成SDRAM时钟信号的非单调性畸变问题。仿真与测量结果表明,在产品研制流程中加入信号完整性仿真环节有利于设计快速收敛,提前规避风险,缩短研发周期,降低设计成本,提高电路产品的可靠性和电磁兼容性。

Rapid Convergence of High-Speed Digital Circuit Design by Using SI Technology

With the continuous improvement of the integration level and operating frequency of the digital circuits, the problem of signal integrity (SI) is becoming more and more prominent in product developing.Aiming at the fault signal loop, the signal integrity of SDRAM clock signal of a navigation computer in inertial navigation system is simulated by using simulation software, and the PCB is optimized.By comparing the simulation and measurement results before and after optimization, the nonmonotonic distortion of SDRAM clock signal due to the mismatch of end connection parameters is verified.The simulation and test results show that the simulation of signal integrity in product developing is benefit to accelerating the convergence of design, avoiding the risk in advance, shortening the development cycle, reducing the designing cost and improving the reliability and electromagnetic compatibility of circuit products.