基于ZYNQ的IRIG-B(DC)码设计与实现

通过对现有的IRIG-B(DC)码授时设备的调查研究发现,有的采用CPLD+AVR MCU实现方案,有的采用FPGA+DSP实现方案,芯片间连线较多,且PCB布线复杂。因此提出了采用ZYNQ器件实现IRIG-B(DC)码,数据交互主要在芯片内部实现,避免了芯片间较多连线,PCB设计简单,面积较小,有利于整机小型化设计。试验结果表明,采用新器件设计的IRIG-B(DC)码输出正常。

Design and Implement of IRIG-B(DC) Code Based on ZYNQ

Through the investigation and research on the existing IRIG-B (DC) code timing equipment, it is found that some of them are realized by CPLD + AVR MCU, some by FPGA + DSP, both with many interchip connections and complex PCB wiring. Therefore, a method of using ZYNQ device to realize IRIG-B (DC) code is proposed. With this method, the data exchange inside the chip, simple PCB design and small area are realised, which avoids many wires between chips, and is conducive to the miniaturization design of the whole system. The test results show that the output of IRIG-B (DC) code designed by the new device is normal.