| BRAM存储器EDAC容错技术可靠性分析 |
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| 引用本文： | 伊小素,邓燕,潘雄,江云天,张家铭.BRAM存储器EDAC容错技术可靠性分析[J].航天控制,2011,29(5):67-71. |
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| 作者姓名： | 伊小素 邓燕 潘雄 江云天 张家铭 |
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| 作者单位： | 北京航空航天大学仪器科学与光电工程学院,北京,100191 |
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| 摘 要： | SRAM型FPGA内部高密度BRAM存储模块作为用户存储资源,在空间运行中易受单粒子翻转效应影响,造成用户数据失效,EDAC技术被广泛采用作为其容错手段.对于商用型SRAM - FPGA,编码/解码模块可靠性对EDAC容错技术有效性具有很大影响,因此本文在考虑编码/解码模块可靠性影响情况下,对商用SRAM - FPGA...
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| 关 键 词： | SEU EDAC 可靠性模型 BRAM |
The BRAM Reliability Analysis with EDAC Fault-Tolerant Technology |
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| YI Xiaosu,DENG Yan,PAN Xiong,JIANG Yuntian,ZHANG Jiaming.The BRAM Reliability Analysis with EDAC Fault-Tolerant Technology[J].Aerospace Control,2011,29(5):67-71. |
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| Authors: | YI Xiaosu DENG Yan PAN Xiong JIANG Yuntian ZHANG Jiaming |
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| Institution: | YI Xiaosu DENG Yan PAN Xiong JIANG Yuntian ZHANG Jiaming School of Instrument Science and Optics-Electronics Engineering,Beijing University of Aeronautics and Astronautics,Beijing 100191,China |
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| Abstract: | In space flight,the embedded high-density BlockRAM memories are susceptible to single-event upsets(SEUs) as the user storage resource in SRAM-based FPGA,which result in failure of the user data.Thus the EDAC technology is widely used as fault-tolerant method.In the development of commercial SRAM-FPGA,the validity of EDAC is affected by the encoding and decoding module.The commercial SRAM-FPGA BRAM memory reliability model with EDAC fault-tolerant technology is proposed,while taking into account the reliabil... |
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| Keywords: | Single-event upset Error detection and correction Reliability model Block RAM |
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