星载FPGA内时序电路设计与时钟控制技术分析

在分析星载FPGA内时序电路特性以及FPGA可编程资源特性的基础上，指出了FPGA内同步时序电路出现时钟偏斜现象的机理。针对时钟偏斜，提出了星载FPGA内时序电路的设计准则。基于设计准则，提出了并行移位寄存器的一种异步化设计方法，阐述了在FPGA源代码中设置设计约束，或在逻辑综合与布局布线过程中联合设置设计约束，将主要同步时序电路时钟信号布置在全局时钟网络上的方法。工程实践表明：上述方法很好地解决了星载FPGA内同步时序电路时钟偏斜问题，可确保星载FPGA工作的稳定性与可靠性。

Analysis of Designing Sequential Circuit and Controlling Clock in FPGA for Spacecraft

Mechanism about the clock skew of synchronism sequential circuit has been presented, based on analyzing the characteristics of programmable resources and sequential circuit in FPGA. In order to cope with the clock skew, a design principle of sequential circuit in FPGA for spacecraft has been provided. Based on the design principle, an asynchronous design of parallel shifting register has been described in detail, and two ways have been presented to put clock signals of main sequential circuit on global clock networks by setting constraints in FPGA design code or in FPGA logic synthesis and layout. Results from the application show that the above-mentioned ways can keep the stability and reliability of FPGA for spacecraft working stably and reliably by solving the problem of clock skew completely.