基于FPGA的串行RS+Viterbi级联译码器的设计与实现

提出了一种基于现场可编程逻辑阵列(FPGA)的RS码(255,223)级联卷积码(4,3,3)译码器及其实现,给出了系统结构。其中级联译码器均采用串行结构,减少了资源占用。卷积译码使用Viterbi算法,给出了其初始化网络、分支度量计算、加比选、累计度量储存、幸存路径储存和回溯等主要部分;RS译码采用欧几里德算法,给出了伴随式计算、错误位置和错误值多项式计算(钱搜索计算错误位置、福尼算法计算错误值)、模二和计算解码输出等关键部分。

Design and Implementation of Serial RS + Viterbi Concatenated Decoder Based on FPGA

The design and implementation of serial RS(255,223) Viterbi(4,3,3) concatenated decoder based on field programmable gate array was put forward in this paper.The system structure was given out.The concatenated decoder was adopted serial structure to reduce the hardware consumption.The Viterbi algorithm was used in convolutional decoding.The major parts of the algorithm,such as initial network,branch measurement calculation,ACS,measurement,surviving path storage and trace back,were introduced.The Euclid algorithm was used in ReedSolomon decoding.The major parts of the algorithm,such as syndrom calculation, multinomial calculation of error position and error value(Chien searching for error position and Forney algorithm for error value),module two and calculated decode output,were also presented.