空间高速总线SpaceWire节点的设计与实现

根据SpaceWire总线的组成结构以及采用的数据-滤波编解码技术,针对SpaceWire节点需要与主机设备、SpaceWire接口设备进行异步交互的特点,文章给出了一种SpaceWire节点的高效实现方案。首先,该方案在硬件设计中采用了SpaceWire节点的多时钟域设计,使得节点整体性能得以显著提升;第二,采用双倍数据速率寄存器设计来降低SpaceWire节点发送端设计难度,解决了高速数据发送问题;第三,采用手动布局接收端的底层器件来满足时序要求,解决了高速数据接收问题;第四,计算出接收端RX FIFO的理论读出时钟频率指导硬件程序设计。在此基础上,采用SpaceWire节点的点对点数据传输实验对文章设计验证,结果表明文章给出的方案可以工作在240MHz时钟频率下,满足空间高速数据传输中高可靠性、低误码率和低复杂度的要求。

The Design and Implementation of Space High-Speed Bus SpaceWire Codec

Based on structure of SpaceWire and the technology of data strobe encoding,and considerating the fact that the node need to asynchronous communicate with host system and SpaceWire equipment,an efficient approach for SpaceWire Codec designing is proposed in this paper.Firstly,multi-clock domains designing method is applied to SpaceWire Codec and its performance is improved greatly.Secondly,the double data rate register is used in the transmitter to reduce designing difficulty and increase the working frequency.Thirdly,the manual layout of FPGA is used in the receiver to meet time requirement of high transmission.Fourthly,the reading frequency of RX FIFO is computed in theory to support hardware design.Finally,the point to point transmission experiment shows that the optimized design can work under 200MHz frequency and meet the requirement of high reliability,fault-tolerance and low complexity.