| SpaceWire软核的设计与验证 |
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| 引用本文： | 刘涛,黄伟,潘卫军.SpaceWire软核的设计与验证[J].航天返回与遥感,2011,32(1):51-58. |
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| 作者姓名： | 刘涛 黄伟 潘卫军 |
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| 作者单位： | 北京空间机电研究所,北京,100076 |
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| 基金项目： | 中国空间技术研究院自主研发课题 |
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| 摘 要： | 介绍了SpaeeWire节点软核在现场可编程门阵列(Field Programmable Gate Array.FPGA)设计与实现中的难点及时钟域划分和模块划分,并针对Virtex-5系列FPGA的特点给出了相应的实现方式.文章设计的SpaceWire 软核在Virtex-5系列FPGA数传电路板上实现了与Space...
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| 关 键 词： | SpaceWire 软核 现场可编程门阵列 |
Design and Verification of Space Wire IP Core |
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| Liu Tao,Huang Wei,Pan Weijun.Design and Verification of Space Wire IP Core[J].Spacecraft Recovery & Remote Sensing,2011,32(1):51-58. |
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| Authors: | Liu Tao Huang Wei Pan Weijun |
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| Institution: | Liu Tao Huang Wei Pan Weijun (Beijing Institute of Space Mechanics & Electricity,Beijing 100076,China) |
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| Abstract: | This paper introduced the key point of design and implementation of SpaceWire IP core in FPGA, and the design of multi-clock,blocking function in FPGA.Based on the characteristics of FPGA of Virtex-5 series,it showed the achievement.It has achieved data transmission between the Space Wire IP core working in the Virtex-5 FPGA development board and the SpaceWire standard test equipment,so high-speed and high-volume data could be transfered.It’s bandwidth can perform up to 300Mbit/s. |
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| Keywords: | SpaceWire |
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