| 基于FPGA的数字存储示波器 |
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| 引用本文： | 周德新,王鹏,范守正,朱鸿林.基于FPGA的数字存储示波器[J].中国民航学院学报,2004,22(2):25-28. |
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| 作者姓名： | 周德新 王鹏 范守正 朱鸿林 |
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| 作者单位： | 中国民用航空学院机电工程学院 天津300300
(周德新，王鹏，范守正)，中国民用航空学院机电工程学院 天津300300(朱鸿林) |
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| 基金项目： | 中国民航学院校科研和教改项目 |
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| 摘 要： | 基于FPGA的数字存储示波器,以可编程逻辑器件ACEX1K30TC144-3和89c51单片机为核心,由通道输入调整、数据采集、数据处理、波形显示和操作面板等功能模块组成.系统中的数据采集及数据处理模块,采用了FPGA内制的RAM IP核,使系统的工作频率基本不受外围器件影响,经maxplusⅡ延时分析,其内核频率可以达到40 MHz以上,这对于数据处理速度和实时性要求比较高的应用领域具有重要的意义.
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| 关 键 词： | 数字存储示波器 单片机 可编程逻辑器件 |
| 文章编号： | 1001-5000(2004)02-0025-04 |
| 修稿时间： | 2003年9月5日 |
Digital Memory Oscillograph Based on FPGA |
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| ZHOU De-xin,WANG Peng,FAN Shou-zheng,ZHU Hong-lin.Digital Memory Oscillograph Based on FPGA[J].Journal of Civil Aviation University of China,2004,22(2):25-28. |
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| Authors: | ZHOU De-xin WANG Peng FAN Shou-zheng ZHU Hong-lin |
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| Abstract: | A kind of memory saving oscillograph based on FPGA could be programmed convertibly into a logic device as a core of ACEX1K30TC144-3 and 89c51 single slice.It consists of path input adjusting,data collecting,wave-form displaying,a front panel as well as a functional modular. FPGA interior core of RAMP is adopted for data collecting and processing modular in the system to an ideal exclusion of disturbance out of irrelevant frequency from alien.Through MAXPLIS II time-delayed analysis,its frequency of the core could be seen as high as 40 MHz or above,which is significant to applications with high expectation to a treatment-speed and to a treatment timing. |
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| Keywords: | FPGA |
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