600Mb/s高速数传接收机的设计与实现

提出一种基于FPGA的600Mb/s高速数传接收机全数字实现方案,对采用Costas环的载波恢复算法和采用并行数据转换跟踪环的码同步算法作了介绍。测试结果表明,该接收机在码速率小于350Mb/s时,解调损失小于1.5dB;在码速率为600Mb/s时,解调损失小于3dB。

Design and Realization of 600Mb/s High Data-rate Receiver

In this paper an all digital solution of 600Mb/s high data-rate receiver(HDRR) on the basis of FPGA is presented.The carrier recovery algorithm which adopts the Costas loop and the bit synchronization algorithm which adopts the parallel data transition tracking loop(DTTL) are expatiated.The test result indicates that when the data rate is no greater than 350Mb/s,the implementation loss of the HDRR is less than 1.5dB,and when the data rate is 600Mb/s,the implementation loss of the HDRR is less than 3dB.