Rapid migration to VLSI

The authors describe how the evolution of digital ASICs from first attempts to VLSI was accelerated in creating a 115000-gate equivalent array, in a 340-pin quad flat pack, within three generations. The first generation consisted of a 7800 gate eq. array containing the `glue logic' for a MIL-STD-1553B, dual redundant serial bus. CAE workstations were used to create the design, and vendor-specific tools were used for final simulations only. The second generation fully embedded the 1553 into the array, along the control registers, timers, counters, interrupt prioritorization and control, memory management, and DNA control circuitry to support an Intel 80960 CPU. The third generation, a 115000 gate eq. array, added a second 1553, three UARTs, and two SDLC serial ports, permitting the creation of a stand-alone computer-I/O card in a single assembly. The third-generation ASIC was created from the second-generation netlist with the addition of vendor-supplied macro circuits, compiled circuits, and synthesized circuits. The utilization of a test vector generation language aided the design process