基于组的点跳跃和编码块并行的JPEG2000位平面扫描方案

研究JPEG2000标准中EBCOT扫描的FPGA实现问题,提出基于组的像素点跳跃和编码块并行两种方案混合使用的EBCOT位平面扫描方案。该设计使用VHDL编写,目标器件为A LTERA STRATIX系列的EP1S25F672C6,模块稳定运行在120MHZ。对于每个并行扫描分路来说,每个时钟周期平均可以产生0.95个上下文信息。分析表明,该设计在图像实时压缩的场合具有优势。

A JPEG2000 Bit-plane Scanning Method Based on Group Columns

The FPGA implenemtation of the EBCOT in JPEG2000 standard is investigated.The GBPS(Group-Based Pixel Skipping)scanning method for EBCOT is presented,and the code-block parallelism method is also used.The architecture is coded in VHDL and the design is targeted to EP1S25F672C6 of Altera Stratix FPGA family.This module can operate at 120MHz steadily.About 0.95 context may be producted by each parallel scan branch in each clock cycle.The analysis indicates that this method has an advantage in the situation of real time image compression.