IEEE1588v2透明时钟研究与实现

主从时钟同步通过普通交换机时，时间同步精度降低且不稳定。为了解决该问题，引入IEEE1588v2中提出透明时钟模型。本文介绍了IEEE1588v2中透明时钟的相关内容，在研究透明时钟基本原理及模型的基础上，提出并实现了在商用交换机上的一种时钟同步扩展方案。为了验证透明时钟的性能，建立模拟真实环境测试平台。测试结果表明在不同的网络背景流量下，透明时钟都能很好地解决非对称延迟及延迟抖动问题，使主从时钟同步精度达到纳秒量级。

Research and Implement of Transparent Clock based on IEEE1588v2

The synchronous packet transmits lends to the problem of asymmetry packet queuing delays and delay jitter by ethernet switch. This problem has a significant impact on IEEE1588 time synchronization precision. To solve it， transparent clock is defined by the IEEE1588v2.In this paper, we introduce transparent clock of IEEE1588v2, proposing a implement scheme of transparent clock based on transparent clock’s principle and model, creating a supporting IEEE1588 ethernet switch with transparent clock. To verify the function of transparent clock, an experimental setup that was analogous to a practical environment. The experiment test results demonstrate that this device efficiently solve the problem of asymmetry packet queuing delays and delay jitter in the condition of different network traffic and the time synchronization precision is at nanosecond level.