基于FPGA的硬件ECC校验的设计与实现

随着存储技术的高速发展,以NAND FLASH为存储介质的存储系统具有存储密度高、容量大、体积小、功耗低和成本低等优点,因此NAND FLASH在不同的领域都得到了广泛的应用。然而,由于NAND FLASH本身的工艺局限性,其数据在传输与存储过程中可能发生"位翻转"的现象,故为了保证存储数据的可靠性,NAND FLASH存储系统在使用过程中需要伴随一定的检错与纠错机制。在对常用的NAND FLASH存储系统校验算法进行简要介绍的基础上,结合NAND FLASH的本身特性,确定在系统中使用ECC校验。对ECC校验的原理及FPGA设计实现进行了阐述,并对设计实现进行了功能仿真和试验验证。

Design and Implementation of ECC Check-out on Hardware Based on FPGA

With the rapid development of storage system, storage system using NAND FLASH has the ad- vantage of high storage density, large capacity, low power and so on. So it has widely used in the different domains. However, NAND FLASH has the character of single bit error, to solve this problem, storage sys- tem with NAND FLASH always uses the check and correct mechanism. This paper firstly introduces some basic concepts and classification of check and correct mechanism in NAND FLASH storage system, then confirms using ECC check- out in this system. The performances analysis, simulation and synthesis result is given at the end of this paper.