| 一种新型高效容错体系结构的研究与实现 |
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| 引用本文： | 陈帆,于海.一种新型高效容错体系结构的研究与实现[J].航空计算技术,2009,39(6):108-111,119. |
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| 作者姓名： | 陈帆 于海 |
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| 作者单位： | 西北工业大学,计算机学院,陕西,西安,710129 |
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| 基金项目： | 国家自然科学基金资助项目 |
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| 摘 要： | 由于辐射而在电路的时序逻辑部分和组合逻辑部分产生的逻辑软错误已经逐渐成为阻碍系统可靠性和稳定性的主要威胁。提出了一种结合了基于主／g．1atch设计和改进的时间冗余策略两种技术的容错体系结构，通过ISCAS’89测试基准电路进行验证并对实验结果的分析发现，该容错体系结构获得了很高的容错性能。
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| 关 键 词： | CMOS技术 软错误 基于latch设计 时间冗余 |
Research and Implementation on an Efficient Logic Soft Errors Tolerant Architecture |
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| CHEN Fan,YU Hai.Research and Implementation on an Efficient Logic Soft Errors Tolerant Architecture[J].Aeronautical Computer Technique,2009,39(6):108-111,119. |
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| Authors: | CHEN Fan YU Hai |
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| Institution: | (College of Computer Science,Northwestern Polytechnical University ,X i ＇an 710129, China) |
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| Abstract: | Logic soft errors are radiation induced transient errors in sequential elements （flip-flops and latches） and combinational logic part. The faults tolerant architecture mentioned in this paper combines latch-based design and time redundancy techniques to achieve high fault tolerant efficiency at low area and speed penalty. ISCAS＇89 benchmark circuits were used as test vehicle to validate the approach. The obtained experiment results show that high fault tolerant efficiency can be achieved by means of meaningful hardware and performance cost. |
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| Keywords: | CMOS technologies soft errors latch- based design time redundancy |
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