开放式FADEC系统的数据总线研究

研究了容错数据总线这个从集中式向开放式架构过渡的关键技术.在深入研究确定性、一致性、开放性、拓扑结构、调度策略、容错机制和传输带宽等开放式FADEC(全权限数字电子控制)数据总线关键特征的基础上,分析了总线数据传输的时间不确定性问题.从性能、可靠性和可用性的角度深入研究了TTP/C(time-triggered protocol/automotive class C),ARINC659,TTCAN(time-triggered controller area network)和FlexRay这4种时间触发架构数据总线的关键特征.研究结果表明:TTP/C总线是开放式FADEC的最佳选择,最后提出了一种基于TTP/C总线的航空发动机模块化DEEC(digital electronic engine controller)硬件架构.

Study on data bus of open FADEC system

The study of fault-tolerant data bus is one of the key technologies for transition from a centralized architecture to a open architecture.The key characteristics of data bus for open FADEC(full authority digital electronic control)system such as consistency,open,transmission bandwidth,scheduling strategies,topologies and fault-tolerant mechanism were studied.Time uncertain problem of bus data transmission was analyzed.The key characteristics of four data bus based on time trigger architecture,which are TTP/C(time-triggered protocol/automotive class C),ARINC659,TTCAN and FlexRay(time-triggered controller area network),were researched from the angle of performance,reliability and availability.The study results show that the TTP/C data buses is the best choice for open FADEC system,and the hardware architecture of modular DEEC (digital electronic engine controller)based on TTP/C data bus was proposed finally.