| 双口RAM在航天伺服系统中的应用 |
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| 引用本文： | 于戈,胡翔宇,曾凡铨,冯伟.双口RAM在航天伺服系统中的应用[J].导航定位于授时,2019,6(5):123-128. |
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| 作者姓名： | 于戈 胡翔宇 曾凡铨 冯伟 |
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| 作者单位： | 上海航天控制技术研究所,上海201109;上海市伺服系统工程技术研究中心,上海201109;上海航天控制技术研究所,上海201109;上海市伺服系统工程技术研究中心,上海201109;上海航天控制技术研究所,上海201109;上海市伺服系统工程技术研究中心,上海201109;上海航天控制技术研究所,上海201109;上海市伺服系统工程技术研究中心,上海201109 |
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| 基金项目： | 上海市伺服系统工程技术研究中心项目（15DZ2250400） |
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| 摘 要： | 航天伺服系统中数据传输具有高速实时等特性，针对采用双口RAM进行并行数据传输时易发生冲突的问题，提出了一种新的数据传输机制。不同于现有握手等待和优先级抢占等方案，从最根本的分时访问总线和数据空间的角度出发，设计了一种同步分时访问机制，实现了无冲突访问数据的高速传输。基于该同步分时访问机制，设计了基于FPGA的双口RAM数据传输方案，并通过仿真验证了该方案的可行性。搭建了数据传输测试平台，设计了多种测试用例。经过测试表明，该双口RAM性能稳定，实现了零误码率数据的高速传输。
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| 关 键 词： | 双口RAM FPGA 同步分时 |
Application of Dual Port RAM in Aerospace Servo System |
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| YU Ge,HU Xiang-yu,ZENG Fan-quan and FENG Wei.Application of Dual Port RAM in Aerospace Servo System[J].Navigation Positioning & Timing,2019,6(5):123-128. |
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| Authors: | YU Ge HU Xiang-yu ZENG Fan-quan and FENG Wei |
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| Institution: | Shanghai Aerospace Control Technology Institute, Shanghai 201109, China;Shanghai Engineering Research Center of Servo System, Shanghai 201109, China,Shanghai Aerospace Control Technology Institute, Shanghai 201109, China;Shanghai Engineering Research Center of Servo System, Shanghai 201109, China,Shanghai Aerospace Control Technology Institute, Shanghai 201109, China;Shanghai Engineering Research Center of Servo System, Shanghai 201109, China and Shanghai Aerospace Control Technology Institute, Shanghai 201109, China;Shanghai Engineering Research Center of Servo System, Shanghai 201109, China |
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| Abstract: | The data transmission in aerospace servo system is characterized by high speed and real time. A new data transmission mechanism is proposed to solve the problem of collision in parallel data transmission using dual port RAM. Different from the existing schemes such as handshake waiting and priority preemption, this paper designs a synchronous time-sharing access mechanism from the perspective of time-sharing access bus and data space to realize high-speed transmission of conflict-free access data. Based on the synchronous time-sharing mechanism, a dual-port RAM data transmission scheme based on FPGA is designed, and the feasibility of the scheme is verified by simulation. The data transmission test platform is set up and a variety of test cases are designed. The full test results show that the dual-port RAM has stable performance and the zero bit error rate data can be transmitted at high speed. |
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| Keywords: | Dual port RAM FPGA Synchronous time-sharing |
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