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CMOS器件单粒子效应电荷收集机理
引用本文:董刚,封国强,陈睿,韩建伟.CMOS器件单粒子效应电荷收集机理[J].北京航空航天大学学报,2014,40(6):839-843.
作者姓名:董刚  封国强  陈睿  韩建伟
作者单位:中国科学院研究生院,北京,100049;中国科学院国家空间科学中心,北京,100190
基金项目:中国科学院支撑技术资助项目(110161501038);中国科学院国家空间科学中心重点培育课题资助项目(Y32113EB3S)
摘    要:针对90 nm CMOS(Complementary Metal Oxide Semiconductor)工艺,采用三维数值模拟方法,研究了反相器中NMOS(Negative channel-Metal-Oxide-Semiconductor)晶体管与PMOS(Positive channel-Metal-Oxide-Semiconductor)晶体管的单粒子瞬变(SET,Single Event Transient)电流脉冲,深入分析了PMOSFET(Positive channel-Metal-Oxide-Semiconductor Field-Effect Transistor)与NMOSFET(Negative channel-Metal-Oxide-Semiconductor Field-Effect Transistor)发生单粒子效应时电荷输运过程和电荷收集机理.研究结果表明,由于电路耦合作用,反相器中晶体管的电荷收集与单个晶体管差异显著;反相器中PMOS晶体管电荷收集过程中存在寄生双极放大效应,NMOS晶体管中不存在寄生双极放大效应;由于双极放大效应,90 nm工艺下PMOS晶体管产生的SET电压脉冲比NMOS晶体管产生的电压脉冲持续时间更长,进而导致PMOS晶体管的SET效应更加敏感.研究结果为数字电路SET的精确建模、进行大规模集成电路SET效应模拟提供了参考依据.

关 键 词:单粒子瞬变  重离子  寄生双极放大效应  反相器  电荷收集  CMOS工艺
收稿时间:2013-07-30

Single event charge collection in CMOS device
Dong Gang,Feng Guoqiang,Chen Rui,Han Jianwei.Single event charge collection in CMOS device[J].Journal of Beijing University of Aeronautics and Astronautics,2014,40(6):839-843.
Authors:Dong Gang  Feng Guoqiang  Chen Rui  Han Jianwei
Abstract:Three dimensions technology computer aided design (3D TCAD) simulation was used to study single event transient (SET) in an invert with 90 nm bulk complementary metal oxide semiconductor (CMOS) technology. The charge transport and charge collection mechanism were analyzed in both positive channel-metal-oxide-semiconductor field-effect transistor (PMOSFET) and negative channel-metal-oxide-semiconductor field-effect transistor (NMOSFET) by numerical simulation. Results show that the radiation induced charge collection mechanism in an inverter device is different from single MOSFET due to coupling circuit effect, and the parasitic bipolar amplification component takes large proportion in charge collection of PMOSFET, but not in NMOSFET. The SET voltage pulse in PMOSFET is wider than NMOSFET and PMOSFET is more sensitive for SET in the submicron technology integrated circuit. The results provide the foundation for SET modeling in digital microcircuits and the model is used for SET simulation in large scale integrated circuits.
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