寄生电感对SiC MOSFET开关特性的影响

随着开关频率的增大,寄生电感对碳化硅(SiC)器件动态开关过程的影响程度也越来越大,无法充分发挥其高速开关下低开关损耗的性能优势。本文采用理论定性分析与实验定量研究相结合的方法,考虑相关寄生电感,对SiC MOSFET基本开关电路建立数学模型,确立影响开关特性的主要因素,然后通过SiC器件高速电路双脉冲测试平台,对各部分寄生电感对SiC器件开关性能的影响进行系统研究,揭示寄生电感对SiC MOSFET开关特性的影响规律。在此基础之上,根据SiC高速开关电路实际布局的限制,在布局紧凑程度或回路走线总长度相对不变的情况下,对各部分寄生电感的匹配关系进行研究,归纳出SiC器件开关过程受寄生参数影响的特性规律,从而指导SiC基高速开关电路的优化布局设计。

Influence of Parasitic Inductance on Switching Characteristics of SiC MOSFET

Parasitic inductance has larger influence on Silicon Carbide devices with the increase of switching frequency. This limits full utilization of performance advantages of low switching losses in high frequency applications. By combining theoretical analysis with experimental parametric study, a mathematic model considering parasitic inductance is developed for the basic switching circuit of SiC MOSFET. Main factors which affect the switching characteristics are explored. Moreover, a fast-switching double-pulse test platform is built to measure individual influence of each parasitic inductance on switching characteristics and guidelines are revealed through experimental results. Due to limits of practical layout in high-speed switching circuits of SiC devices, the matching relations are developed and an optimized layout design method of parasitic inductance is proposed under a constant length of the switching loop. The design criteria are concluded based on the impact of parasitic inductance, which provide guidelines for layout design considerations for SiC-based high-speed switching circuits.