| 基于TTP/C总线的开放式DEEC设计及PIL仿真验证 |
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| 引用本文： | 陈建,刘冬冬,张天宏.基于TTP/C总线的开放式DEEC设计及PIL仿真验证[J].航空动力学报,2014,29(12):2936-2941. |
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| 作者姓名： | 陈建 刘冬冬 张天宏 |
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| 作者单位： | 南京航空航天大学 能源与动力学院 江苏省航空动力系统重点实验室, 南京 210016;中国航空工业集团公司 航空动力控制系统研究所, 江苏 无锡 214063;南京航空航天大学 能源与动力学院 江苏省航空动力系统重点实验室, 南京 210016;中国航空工业集团公司 航空动力控制系统研究所, 江苏 无锡 214063;南京航空航天大学 能源与动力学院 江苏省航空动力系统重点实验室, 南京 210016 |
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| 基金项目： | 江苏省优势学科资助项目 |
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| 摘 要： | 基于自主设计的TTP/C(时间触发协议)总线控制器,提出了开放式DEEC(发动机数字式电子控制器)的冗余架构,将其划分为输入、核心计算及输出3种智能节点,并制定了各个智能节点的任务调度规划图.设计了基于DSP(digital signal processor)+FPGA(field-programmable gate array)的智能节点硬件平台,在此基础上完成各智能节点的软件设计.最后构建了开放式DEEC的PIL(process in the loop)仿真测试平台,以发动机模型为控制对象,展开了状态调节试验和总线故障注入试验.试验结果证明该开放式DEEC是可行的,并具有良好的重构特性.
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| 关 键 词： | 发动机数字式电子控制器 TTP/C总线 开放式架构 PIL仿真 重构 |
| 收稿时间： | 2013/7/21 0:00:00 |
Design of open DEEC based on TTP/C bus and verification of PIL simulation |
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| CHEN Jian,LIU Dong-dong and ZHANG Tian-hong.Design of open DEEC based on TTP/C bus and verification of PIL simulation[J].Journal of Aerospace Power,2014,29(12):2936-2941. |
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| Authors: | CHEN Jian LIU Dong-dong and ZHANG Tian-hong |
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| Affiliation: | Jiangsu Province Key Laboratory of Aerospace Power System, College of Energy and Power Engineering, Nanjing University of Aeronautics and Astronautics, Nanjing 210016, China;Aviation Motor Control System Institute, Aviation Industry Corporation of China, Wuxi Jiangsu 214063, China;Jiangsu Province Key Laboratory of Aerospace Power System, College of Energy and Power Engineering, Nanjing University of Aeronautics and Astronautics, Nanjing 210016, China;Aviation Motor Control System Institute, Aviation Industry Corporation of China, Wuxi Jiangsu 214063, China;Jiangsu Province Key Laboratory of Aerospace Power System, College of Energy and Power Engineering, Nanjing University of Aeronautics and Astronautics, Nanjing 210016, China |
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| Abstract: | With the self-development TTP/C (time trigger protocol/automotive class C) bus controller, a redundant architecture of open DEEC (digital electronic engine controller) was proposed, which was divided into three kinds of intelligent nodes: input, core calculation and output, and the task scheduling for each intelligent node was planned. Hardware platform of intelligent node was designed based on DSP (digital signal processor) and FPGA (field-programmable gate array), and the software was designed for each intelligent node. Finally, a PIL (process in the loop) simulation test platform for open DEEC was constructed.With an engine model as the controlled object, the state regulation experiments and bus fault injection experiments were conducted.The experiment results show that the open DEEC architecture is feasible and has a good reconstruction ability. |
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| Keywords: | DEEC TTP/C bus open architecture PIL simulation reconstruction |
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